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19-1580; Rev 0; 12/99
Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs
General Description
The MAX5188 is a dual 8-bit, alternate-phase-update, current-output digital-to-analog converter (DAC) designed for superior performance in systems requiring analog signal reconstruction with low distortion and low-power operation. The MAX5191 provides equal specifications, with on-chip output resistors for voltageoutput operation. Both devices are designed for 10pVs glitch operation to reduce distortion and minimize unwanted spurious signal components at the output. An on-board +1.2V bandgap circuit provides a well-regulated, low-noise reference that may be disabled for external reference operation. The MAX5188/MAX5191 are designed to provide a high level of signal integrity for the least amount of power dissipation. Both DACs operate from a +2.7V to +3.3V single supply. Additionally, these DACs have three modes of operation: normal, low-power standby, and full shutdown. A full shutdown provides the lowest possible power dissipation with a maximum shutdown current of 1A. A fast wake-up time (0.5s) from standby mode to full DAC operation allows for power conservation by activating the DACs only when required. The MAX5188/MAX5191 are available in a 28-pin QSOP package and are specified for the extended (-40C to +85C) temperature range. For pin-compatible 10-bit versions, refer to the MAX5182/MAX5185 data sheet.
Features
o +2.7V to +3.3V Single-Supply Operation o Wide Spurious-Free Dynamic Range: 70dB at fOUT = 2.2MHz o Fully Differential Outputs for Each DAC o 0.5% FSR Gain Mismatch Between DAC Outputs o Low-Current Standby or Full Shutdown Modes o Internal +1.2V Low-Noise Bandgap Reference o Small 28-Pin QSOP Package
MAX5188/MAX5191
Ordering Information
PART MAX5188BEEI MAX5191BEEI TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 QSOP 28 QSOP
Pin Configuration Applications
Signal Reconstruction Applications Digital Signal Processing Arbitrary Waveform Generators Imaging Applications
TOP VIEW
CREF1 1 OUT1P 2 OUT1N 3 AGND 4 AVDD 5 DACEN 6 PD 7 CS 8 CLK 9 N.C. 10 REN 11 DGND 12 DGND 13 D0 14 28 CREF2 27 OUT2P 26 OUT2N 25 REFO 24 REFR
MAX5188 MAX5191
23 DGND 22 DVDD 21 D7 20 D6 19 D5 18 D4 17 D3 16 D2 15 D1
QSOP ________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD to AGND, DGND .................................-0.3V to +6V Digital Inputs to DGND.............................................-0.3V to +6V OUT1P, OUT1N, OUT2P, OUT2N, CREF1, CREF2 to AGND ....................................................-0.3V to +6V VREF to AGND ..........................................................-0.3V to +6V AVDD to DVDD .....................................................................3.3V AGND to DGND.....................................................-0.3V to +0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 28-Pin QSOP (derate 9.00mW/C above +70C)..........725mW Operating Temperature Ranges MAX5188/MAX5191BEEI ..................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +3V 10%, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400 differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Zero-Scale Error Full-Scale Error DYNAMIC PERFORMANCE Output Settling Time Glitch Impulse Spurious-Free Dynamic Range to Nyquist Total Harmonic Distortion to Nyquist Signal-to-Noise Ratio to Nyquist DAC-to-DAC Output Isolation Clock and Data Feedthrough Output Noise Gain Mismatch Between DAC Outputs ANALOG OUTPUT Full-Scale Output Voltage Voltage Compliance of Output Output Leakage Current Full-Scale Output Current DAC External Output Resistor Load 2 IFS DACEN = 0, MAX5188 only MAX5188 only MAX5188 only VFS -0.3 -1 0.5 1 400 400 0.8 1 1.5 mV V A mA fOUT = 2.2MHz SFDR THD SNR fCLK = 40MHz fCLK = 40MHz fCLK = 40MHz fOUT = 2.2MHz All 0s to all 1s fOUT = 550kHz fOUT = 2.2MHz fOUT = 550kHz fOUT = 2.2MHz fOUT = 550kHz fOUT = 2.2MHz 46 57 To 0.5LSB error band 25 10 72 70 -70 -68 52 52 -60 50 10 0.5 1 -63 ns pVs dBc dB dB dB nVs pA/Hz LSB N INL DNL Guaranteed monotonic MAX5188 MAX5191 (Note 1) 8 -1 -1 -1 -4 -20 4 0.25 0.25 +1 +1 +1 +4 +20 Bits LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
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Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +3V 10%, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400 differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER REFERENCE Output Voltage Range Output Voltage Temperature Drift Reference Output Drive Capability Reference Supply Rejection Current Gain (IFS / IREF) POWER REQUIREMENTS Analog Power-Supply Voltage Analog Supply Current Digital Power-Supply Voltage Digital Supply Current Standby Current Shutdown Current LOGIC INPUTS AND OUTPUTS Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Input Capacitance TIMING CHARACTERISTICS DAC1 DATA to CLK Rise Setup Time DAC2 DATA to CLK Fall Setup Time DAC1 CLK Rise to DATA Hold Time DAC2 CLK Fall to DATA Hold Time CS Fall to CLK Rise Time CS Fall to CLK Fall Time DACEN Rise Time to VOUT PD Fall Time to VOUT Clock Period Clock High Time Clock Low Time tCLK tCH tCL 25 10 10 tDS1 tDS2 tDH1 tDH2 10 10 0 0 5 5 0.5 50 ns ns ns ns ns ns s s ns ns ns VIH VIL IIN CIN VIN = 0 or DVDD 10 2 0.8 1 V V A pF AVDD IAVDD DVDD IDVDD ISTANDBY ISHDN PD = 0, DACEN = 1, digital inputs at 0 or DVDD PD = 0, DACEN = 0, digital inputs at 0 or DVDD PD = 1, DACEN = X, digital inputs at 0 or DVDD (X = don't care) PD = 0, DACEN = 1, digital inputs at 0 or DVDD 2.7 4.2 1 0.5 2.7 2.7 3.3 5 3.3 5 1.5 1 V mA V mA mA A VREF TCVREF IREFOUT 1.12 1.2 50 10 0.5 8 1.28 V ppm/C A mV/V mA/mA SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Excludes reference and reference resistor (MAX5191) tolerance.
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3
Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
Typical Operating Characteristics
(AVDD = DVDD = +3V, AGND = DGND = 0, 400 differential output, IFS = 1mA, CL = 5pF, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. INPUT CODE
MAX5188/91-01
DIFFERENTIAL NONLINEARITY vs. INPUT CODE
MAX5188/91-02
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5188/91-03
0.150 0.125 0.100 0.075 INL (LSB)
0.100 0.075 0.050 DNL (LSB) 0.025 0 -0.025 -0.050 -0.075
3.00 ANALOG SUPPLY CURRENT (mA)
2.75
MAX5191
0.050 0.025 0
2.50
MAX5188
2.25
-0.025 -0.050 0 32 64 96 128 160 192 224 256 INPUT CODE
2.00 0 32 64 96 128 160 192 224 256 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT CODE SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5188/91-04
DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5188/91-05
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX5188/91-06
3.00 ANALOG SUPPLY CURRENT (mA)
10 DIGITAL SUPPLY CURRENT (mA)
4.00 DIGITAL SUPPLY CURRENT (mA) MAX5188 3.75 MAX5191 3.50
2.75
MAX5191
8 6 MAX5188 MAX5191 4 2
2.50
MAX5188
2.25
3.25
2.00 -40 -15 10 35 60 85 TEMPERATURE (C)
0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
3.00 -40 -15 10 35 60 85 TEMPERATURE (C)
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX5188/91-07
STANDBY CURRENT vs. TEMPERATURE
MAX5188/91-08
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
MAX5188/91-09
620 610 STANDBY CURRENT (A) MAX5191 600 590 MAX5188 580 570 560 2.5 3.0 3.5 4.0 4.5 5.0
600 MAX5191 590 STANDBY CURRENT (A)
3.8
SHUTDOWN CURRENT (A)
3.7
580
3.6
MAX5188 MAX5191
570
MAX5188
3.5
560
550 5.5 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (C)
3.4 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
4
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Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs
Typical Operating Characteristics (continued)
(AVDD = DVDD = +3V, AGND = DGND = 0, 400 differential output, IFS = 1mA, CL = 5pF, TA = +25C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX5188/91-11
MAX5188/MAX5191
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX5188/91-12
OUTPUT CURRENT vs. REFERENCE CURRENT
MAX5188/91-13
1.28
1.28
4
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1.26 MAX5188 1.25 MAX5191 1.24
1.26 MAX5188 MAX5191 1.24
OUTPUT CURRENT (mA)
1.27
1.27
3
2
1.25
1
1.23 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
1.23 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 100 200 300 400 500 REFERENCE CURRENT (A)
DYNAMIC RESPONSE RISE TIME
MAX5188/91-14
DYNAMIC RESPONSE FALL TIME
MAX5188/91-15
OUT_P 150mV/div
OUT_P 150mV/div
OUT_N 150mV/div
OUT_N 150mV/div
50ns/div
50ns/div
SETTLING TIME
MAX5188/91-16
FFT PLOT, DAC1
MAX5188/91-17
FFT PLOT, DAC2
fCLK = 40MHz fOUT = 2.2MHz
MAX5188/91-18
0 -10 -20 -30 -40 -50 -60 -70 -80
fCLK = 40MHz fOUT = 2.2MHz
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
OUT_N 100mV/div (dBc)
OUT_P 100mV/div
-90 -100 -110 -120 12.5ns/div 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY (MHz)
(dBc)
0
2
4
6
8
10 12 14 16 18 20
OUTPUT FREQUENCY (MHz)
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Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
Typical Operating Characteristics (continued)
(AVDD = DVDD = +3V, AGND = DGND = 0, 400 differential output, IFS = 1mA, CL = 5pF, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY
MAX5188/91-19
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY AND CLOCK FREQUENCY, DAC1
fCLK = 40MHz fCLK = 60MHz
MAX5188/91-20
100 90 80 SFDR (dBc) DAC2 70 60 50 40 DAC1
78 76 74 SFDR (dBc) 72 fCLK = 50MHz 70 fCLK = 10MHz 68 fCLK = 30MHz 66
fCLK = 20MHz
10 15 20 25 30 35 40 45 50 55 60 CLOCK FREQUENCY (MHz)
500 700 900 1100 1300 1500 1700 1900 2100 2300 OUTPUT FREQUENCY (kHz)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY AND CLOCK FREQUENCY, DAC2
MAX5188/91-21
SIGNAL-TO-NOISE PLUS DISTORTION vs. OUTPUT FREQUENCY
MAX5188/91-23
78 fCLK = 50MHz fCLK = 20MHz fCLK = 40MHz 76 74 SFDR (dBc)
62.5
62.0
SINAD (dB)
61.5
DAC2 DAC1
72 70 68 66 500 700 900 1100 1300 1500 1700 1900 2100 2300 OUTPUT FREQUENCY (kHz) fCLK = 10MHz fCLK = 60MHz
61.0
60.5 fCLK = 30MHz 60.0 0 500 1000 1500 2000 2500 OUPUT FREQUENCY (kHz)
MULTITONE SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY
-10 -20 -30 SFDR (dBc) -40 -50 -60 -70 -80 -120 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY (MHz) 62 60 0.50
MAX5188/91-24
SPURIOUS-FREE DYNAMIC RANGE vs. FULL-SCALE OUTPUT CURRENT
MAX5188/91-26
0
74 72 70 SFDR (dBc) 68 66 64
0.75
1.00
1.25
1.50
FULL-SCALE OUTPUT CURRENT (mA)
6
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Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs
Pin Description
PIN 1 2 3 4 5 NAME CREF1 OUT1P OUT1N AGND AVDD Reference Bias Bypass, DAC1 Positive Analog Output, DAC1. Current output for the MAX5188; voltage output for the MAX5191. Negative Analog Output, DAC1. Current output for the MAX5188; voltage output for the MAX5191. Analog Ground Analog Positive Supply, +2.7V to +3.3V DAC Enable, Digital Input 0: Enter DAC standby mode with PD = DGND 1: Power-up DAC with PD = DGND X: Enter shutdown mode with PD = DVDD (X = don't care) Power-Down Select 0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD) 1: Enter shutdown mode Active-Low Chip Select Clock Input Not Connected. Do not connect to this pin. Active-Low Reference Enable. Connect to DGND to activate on-chip +1.2V reference. Digital Ground Data Bit D0 (LSB) Data Bits D1-D6 Data Bit D7 (MSB) Digital Supply, +2.7V to +3.3V Reference Input Reference Output Negative Analog Output, DAC2. Current output for the MAX5188; voltage output for the MAX5191. Positive Analog Output, DAC2. Current output for the MAX5188; voltage output for the MAX5191. Reference Bias Bypass, DAC2 FUNCTION
MAX5188/MAX5191
6
DACEN
7 8 9 10 11 12, 13, 23 14 15-20 21 22 24 25 26 27 28
PD CS CLK N.C. REN DGND D0 D1-D6 D7 DVDD REFR REFO OUT2N OUT2P CREF2
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Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
REN 1.2V REF REFO REFR CURRENTSOURCE ARRAY AVDD AGND CS DACEN PD
CREF1 CREF2
9.6k* DAC 1 SWITCHES DAC 2 SWITCHES
OUT1P OUT1N OUT2P OUT2N
400*
400*
OUTPUT LATCHES MSB DECODE CLK INPUT LATCHES
OUTPUT LATCHES MSB DECODE INPUT LATCHES
400*
MAX5188 MAX5191
DVDD DGND
*INTERNAL 400 AND 9.6k RESISTORS FOR MAX5191 ONLY.
D7-D0
Figure 1. Functional Diagram
Detailed Description
The MAX5188/MAX5191 are dual 8-bit digital-to-analog converters (DACs) capable of operating with clock speeds up to 40MHz. Each of these dual converters consists of separate input and DAC registers, followed by a current-source array capable of generating up to 1.5mA full-scale output current (Figure 1). An integrated +1.2V voltage reference and control amplifier determine the data converters' full-scale output currents/ voltages. Careful reference design ensures close gain matching and excellent drift characteristics. The MAX5191's voltage output operation features matched 400 on-chip resistors that convert the current from the current array into a voltage.
Due to its limited 10A output drive capability, the REFO pin must be buffered with an external amplifier if heavier loading is required. The MAX5188/MAX5191 also employ a control amplifier, designed to simultaneously regulate the full-scale output current IFS for both MAX5188/MAX5191 outputs. The output current is calculated as follows: IFS = 8 * IREF where I REF is the reference output current (I REF = VREFO / RSET) and IFS is the full-scale output current. R SET is the reference resistor that determines the amplifier's output current (Figure 2) on the MAX5188. This current is mirrored into the current-source array, where it is equally distributed between matched current segments and summed to valid output current readings for the DACs. Inside the MAX5191, each output current (DAC1 and DAC2) is converted to an output voltage (V OUT1 , VOUT2) with two internal, ground-referenced, 400 load resistors. Using the internal +1.2V reference voltage, the integrated reference output current resistor of the MAX5191 (RSET = 9.6k) sets IREF to 125A and IFS to 1mA.
Internal Reference and Control Amplifier
The MAX5188/MAX5191 provide an integrated 50ppm/C, +1.2V, low-noise bandgap reference that can be disabled and overridden by an external reference voltage. REFO serves either as an input for an external reference or as an output for the integrated reference. If REN is connected to DGND, the internal reference is selected and REFO provides a +1.2V output.
8
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400*
Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS REN MAX4040 +1.2V BANDGAP REFERENCE REFO CCOMP* AGND VREF RSET AGND REFR CURRENTSOURCE ARRAY IFS DGND
IREF
IREF =
RSET
RSET** 9.6k
MAX5188 MAX5191
*COMPENSATION CAPACITOR (CCOMP = 100nF)
**9.6k REFERENCE CURRENT SET RESISTOR INTERNAL TO MAX5191 ONLY. USE EXTERNAL RSET FOR MAX5188.
Figure 2. Setting IFS with the Internal +1.2V Reference and Control Amplifier
External Reference
To disable the MAX5188/MAX5191's internal reference, connect REN to DVDD. A temperature-stable external reference may now be applied to drive the REFO pin (Figure 3) to set the full-scale output. Choose a reference that can supply at least 150A to drive the bias circuit that generates the cascode current for the current array. For improved accuracy and drift performance, choose a fixed output voltage reference such as the +1.2V, 25ppm/C MAX6520 bandgap reference.
must be pulled high with PD held at DGND. The MAX5188/MAX5191 typically require 50s to wake up and allow both the outputs and the reference to settle.
Shutdown Mode
For lowest power consumption, the MAX5188/MAX5191 provide a power-down mode in which the reference, control amplifier, and current array are inactive and the DAC's supply current is reduced to 1A. To enter this mode, connect PD to DVDD. To return to active mode, connect PD to DGND and DACEN to DVDD. About 50s are required for the devices to leave shutdown mode and settle their outputs to the values prior to shutdown. Table 1 lists the power-down mode selection.
Standby Mode
To enter the lower-power standby mode, connect digital inputs PD and DACEN to DGND. In standby, both the reference and the control amplifier are active with the current array inactive. To exit this condition, DACEN
Table 1. Power-Down Mode Selection
PD (POWER-DOWN SELECT) 0 0 1 X = Don't care _______________________________________________________________________________________ 9 DACEN (DAC ENABLE) 0 1 X POWER-DOWN MODE Standby Wake-Up Shutdown MAX5188 MAX5191 MAX5188 MAX5191 OUTPUT STATE High-Z AGND High-Z AGND
Last state prior to standby mode
Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
DVDD 10F REN +1.2V BANDGAP REFERENCE REFO CURRENTSOURCE ARRAY IREF RSET 9.6k* IFS DGND 0.1F
AVDD
EXTERNAL +1.2V REFERENCE
REFR
MAX6520
AGND
AGND
MAX5188 MAX5191
*9.6k REFERENCE CURRENT SET RESISTOR INTERNAL TO MAX5191 ONLY. USE EXTERNAL RSET FOR MAX5188.
Figure 3. MAX5188/MAX5191 Using an External Reference
tCLK
tCL
tCH
CLK N-1 D0-D7 tDS1 DAC1 tDS2 DAC2 N-1 DAC1 tDH1 N DAC2 tDH2 N DAC1 N+1 DAC2 N+1
OUT1
N-1
N
N+1
OUT2
N-1
N
N+1
Figure 4. Timing Diagram
10
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Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs
Timing Information
Both internal DAC cells write to their outputs in alternate phase (Figure 4). The input latch of the first DAC (DAC1) is loaded after the clock signal transitions high. When the clock signal transitions low, the input latch of the second DAC (DAC2) is loaded. The contents of the first input latch are shifted into the DAC1 register on the rising edge of the clock; the contents of the second input latch are shifted into the input register of DAC2 on the falling edge of the clock. Both outputs are updated on alternate phases of the clock. ed 400 resistors that restore the array currents into proportional, differential voltages of 400mV. These differential output voltages can then be used to drive a balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a single-ended voltage.
MAX5188/MAX5191
Applications Information
Static and Dynamic Performance Definitions
Integral Nonlinearity Integral nonlinearity (INL) (Figure 5a) is the deviation of the values on an actual transfer function from either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints
Outputs
The MAX5188 outputs are designed to supply 1mA fullscale output currents into 400 loads in parallel with a capacitive load of 5pF. The MAX5191 features integrat-
7 6 6 ANALOG OUTPUT VALUE 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (1/4 LSB ) AT STEP 011 (1/2 LSB ) ANALOG OUTPUT VALUE 5 4 3 1 LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+1/4 LSB) 1 LSB DIFFERENTIAL LINEARITY ERROR (-1/4 LSB)
Figure 5a. Integral Nonlinearity
Figure 5b. Differential Nonlinearity
3 ANALOG OUTPUT VALUE
ACTUAL DIAGRAM ANALOG OUTPUT VALUE
7
IDEAL FULL-SCALE OUTPUT GAIN ERROR (-1 1/4 LSB)
6 IDEAL DIAGRAM 5 ACTUAL FULL-SCALE OUTPUT
2 IDEAL DIAGRAM 1 ACTUAL OFFSET POINT IDEAL OFFSET POINT 000 001
OFFSET ERROR (+1 1/4 LSB)
4 0
0
010
011
000 100
101
110
111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 5c. Offset Error
Figure 5d. Gain Error 11
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Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
of the transfer function once offset and gain errors have been nullified. For a DAC, the deviations are measured at every single step. Differential Nonlinearity Differential nonlinearity (DNL) (Figure 5b) is the difference between an actual step height and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Offset Error Offset error (Figure 5c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated by trimming. Gain Error Gain error (Figure 5d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter's specified accuracy. Digital Feedthrough Digital feedthrough is the noise generated on a DAC's output when any digital input transitions. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal's first five harmonics to the fundamental itself. This is expressed as: THD = 20
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high input-bandwidth amplifier may be used to generate a voltage from the MAX5188's current-array output. The differential voltage across OUT1P (or OUT2P) and OUT1N (or OUT2N) is converted into a single-ended voltage by designing an appropriate operational amplifier configuration as shown in Figure 6.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influence the performance of the MAX5188/MAX5191. Unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections, which may affect dynamic specifications like SNR or SFDR. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5188/MAX5191. Therefore, grounding and powersupply decoupling guidelines for high-speed, high-frequency applications should be closely followed. First, a multilayer PC board with separate ground and power-supply planes is recommended. High-speed signals should run on controlled impedance lines directly above the ground plane. Since the MAX5188/ MAX5191 have separate analog and digital ground buses (AGND and DGND, respectively), the PC board should also have separate analog and digital ground sections with only one point connecting the two. Digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. Both devices have two power-supply inputs: analog VDD (AVDD) and digital VDD (DVDD). Each AVDD input should be decoupled with parallel 10F and 0.1F ceramic-chip capacitors as close to the pin as possible. Their opposite ends should have the shortest possible connection to the ground plane. The DVDD pins should also have separate 10F and 0.1F capacitors, again adjacent to their respective pins. Try to minimize the analog load capacitance for proper operation. For best performance, bypass CREF1 and CREF2 with lowESR, 0.1F capacitors to AVDD. The power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi network could also improve performance.
log
(V22 + V32 + V42 + V52 )
V1
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component.
12
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Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
AVDD +3V 10F 0.1F 0.1F 10F 0.1F AVDD CLK DVDD CREF1 CREF2 OUT1P OUTPUT1 400* 402 402 +5V 0.1F AVDD
+3V
D0-D7
MAX5188 MAX5191
OUT1N 402 400* 402 REFO 402 OUT2P
-5V 402
MAX4108
+5V OUTPUT2
0.1F
400* REFR RSET** OUT2N 402 400* DGND REN AGND 402 -5V
MAX4108
**MAX5188 ONLY *400 RESISTORS INTERNAL TO MAX5191 ONLY.
Figure 6. Differential to Single-Ended Conversion Using the MAX4108 Low-Distortion Amplifier
Chip Information
TRANSISTOR COUNT: 9464 SUBSTRATE CONNECTED TO GND
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13
Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
Package Information
QSOP.EPS
14
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Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
NOTES
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15
Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs MAX5188/MAX5191
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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Price & Availability of MAX5188

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